EDN

How to build ultra-fast floating-point FFTs in FPGAs

Engineers targeting DSP to FPGAs have traditionally used fixed-point arithmetic, mainly because of the high cost associated with implementing floating-point arithmetic. That cost comes in the form of ...
EDN

Fixed vs. floating point: a surprisingly hard choice

[Editor's note: For an intro to floating-point math, see Tutorial: Floating-point arithmetic on FPGAs. For an intro to fixed-point math, see Fixed-Point DSP and Algorithm Implementation.] The ...
Design-Reuse

Altera Introduces Industry's First FPGA Floating-Point FFT IP Cores

New Cores Leverage Stratix Device Family's Embedded DSP Blocks to Deliver a Cost-Effective Floating-Point FFT FPGA Solution San Jose, Calif., June 3, 2003—Altera Corporation (NASDAQ: ALTR) today ...
Design-Reuse

Accelerating Fixed-Point Design for MB-OFDM UWB Systems

Ultrawideband (UWB) wireless technology is poised to replace high-speed data cables in homes and offices. 1 UWB technology will be capable of transmitting hundreds of megabits per second over ...