Hackaday

Moving An FPGA Project From VGA To DVI-D

It’s fairly easy to create VGA with an FPGA using a simple R/2R DAC. As [Mike] points out, this requires a lot of IO pins, and many development boards only support 8 bit VGA. Analog VGA is being ...
Hackaday

FPGA Used VHDL For Fractals

Over on GitHub, [ttsiodras] wanted to learn VHDL. So he started with an algorithm to do Mandelbrot sets and moved it to an FPGA. Because of the speed, he was able to accomplish real-time zooming. You ...
EDN

Improve FPGA project management/test by eschewing the IDE

A common way to do an FPGA design is to create a project using your design tool. A project consists of a hierarchy of directories and many files. Creating a project, you have a nice GUI, wizards, and ...
Semiconductor Engineering

Trends In FPGA Verification Effort And Adoption: The 2018 Wilson Research Group Functional Verification Study

As contributors and pioneers in the digital revolution, we are often so busy creating and innovating that we are compelled to focus on the trees, never mind the forest. But as we are all aware, the ...
The Droid Guy

Hands On With Mars FPGA A Powerhouse Development Board Tutorial

The MARS FPGA is an ambitious, open-source project designed to surpass the capabilities of existing FPGA-based retro gaming systems, particularly the MiSTer FPGA. This powerhouse development board ...
Geeky Gadgets

µLab Kiwi and Kiwi Lite FPGA programming board

Soon to be launching via the Crowd Supply website are two new FPGA programming boards taking the form of the µLab Kiwi and Kiwi Lite. The project has launched as yet but you can jump over to the ...
EDN

ST halts open-source FPGA project

SANTA CRUZ, Calif. — Pulling the plug on an ambitious open-source FPGA hardware and software project, ST Microelectronics confirmed Tuesday (April 26) it will stop development of its Generalized Open ...
Semiconductor Engineering

Verification Effectiveness In The Face Of FPGA Complexity: The 2020 Wilson Research Group Functional Verification Study

Making informed decisions backed by good data is the key to success in highly competitive, robust markets such as FPGA design and verification. Helping our community in that endeavor is the motivation ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.